The present invention relates to a semiconductor device equipped with a memory cells that need a refresh operation for storing data.
FIG. 12 shows the architecture of a conventional DRAM. In FIG. 12, a memory cell array 1001 includes a large number of memory cells arranged in a row direction and a column direction; a plurality of pairs of bit lines connected to these memory cells and extending in the column direction; a plurality of sense amplifiers arranged in the row direction for amplifying data on these bit line pairs; and 8n pairs of data lines 1001a arranged in the column direction. Also, a 1/8 selection circuit 1002 selects n pairs of data lines 1001a from the 8n pairs of data lines. A read amplifier 1003 amplifies data on the n pairs of data lines selected by the 1/8 selection circuit 1002 and outputs the amplified data to the outside. A write amplifier 1004 receives input data from a latch 1005 for latching the input data (writing data) of n bits and amplifies the input data.
The page-mode read operation and the page-mode write operation of such a DRAM will now be described. FIG. 13 is a timing chart for the conventional page-mode read operation and FIG. 14 is a timing chart for the conventional page-mode write operation. First, the conventional page-mode read operation will be described. In FIG. 13, data of memory cells selected in the memory cell may 1001 is amplified by the sense amplifiers to be output to the 8n pairs of data lines 1100a through the bit line pairs in a time t1. Out of the data on the 8n pairs of data lines 1100a, n pairs of data is selected by the 1/8 selection circuit 1002, and the selected data is amplified by the read amplifier 1003 to be output to the outside. In each of times t2, t3 and t4, data of n bits is output to the outside through the same processing as that performed in the time t1.
Next, the conventional page-mode write operation will be described. In FIG. 14, the input data of n bits latched by the latch 1005 is amplified by the write amplifier 1004, and the amplified data is written, through n pairs of data lines 1100a selected by the 1/8 selection circuit 1002, in memory cells selected in the memory cell array 1100a in a time t1. In each of times t2, t3 and t4, input data is written in selected memory cells through the same processing as that performed in the time t1.
Furthermore, for example, Japanese Laid-Open Patent Publication No. 5-6659 discloses another conventional DRAM in which a plurality of row buffers are provided, each for one row specified by a row address, data of a memory cell array is transferred to a specified buffer out of the plural row buffers in making a normal memory access, data is output from the specified row buffer in a page-mode read operation and data is written in the specified row buffer in a page-mode write operation.
In both of the two types of conventional DRAMs, however, the memory cell array is in an active state during a page-mode cycle, and therefore, a refresh operation for memory cells cannot be performed during this period. Therefore, in the case where a charge holding time of a memory cell is short as in a pure CMOS DRAM, an interval between the refresh operations is long in making a long page access, and hence, it is disadvantageously difficult to hold data.